1. Field of the Invention
The present invention relates to semiconductor wafer arrays in general and in particular to a method and apparatus comprising a stacked array of semiconductor wafers which are interconnected by means of an electrically conductive liquid.
2. Description of the Prior Art
Since the development of integrated circuit technology, computers and computer storage devices have been made from wafers of semiconductor material comprising a plurality of integrated transistor circuits. After the wafer is made, the circuits are separated from each other by cutting the wafer into small chips. Thereafter, the chips are bonded to carriers of varying types, interconnected by tiny wires and packaged.
The above-described process of making computers and computer memory devices has been found to be time-consuming and costly and the use of tiny wires to electrically connect the chips has often been found to be unreliable. Moreover, the length of the wires which has been required to make the necessary interconnections between chips has been found to result in undesirable signal delays as the frequency of operation of the devices has increased.
To avoid some of the disadvantages of the prior technology, a number of efforts have been made to eliminate the need for separating chips in a wafer and interconnecting them using wires. For example, a technology called Wafer Scale Integration (WSI) attempted to do this. In WSI, techniques were used to wire together all the chips on a single wafer; however, the attempts thus far have not been successful. It was found that the line widths required to provide a computer on a single wafer, even when multiple layers of lateral connections were used, became so small that it was not possible to obtain lines of sufficient length and precision to make the necessary interconnections between the circuits therein.
The use of WSI technology which uses lateral connections to connect the circuits on a single wafer also has disadvantages when used for making storage devices. In practice, all wafers comprise randomly located defects. The defects render the circuits affected unusable. Since WSI technology incorporates the defective circuits at the time a wafer is made, it is difficult and costly to build in an amount of redundancy sufficient to overcome the effect of the defects. In any event, even if a single wafer comprising a large number of storage cells could be built at a reasonable cost, the memory capacity required in many applications far exceeds that which can be provided on a single wafer. Therefore, such applications would still require that a plurality of such wafers be used and that the wafers be interconnected in some suitable manner.
Other attempts to avoid the disadvantages of interconnecting a plurality of stacked wafers using wires have involved large scale parallel array processors and memory devices in which parallel circuit members are interconnected using vertical columns of solid, dense conductive material such as solder, copper, etc. For example, in U.S. Pat. No. 4,368,106, there is disclosed a process for making a solid, dense metallic feedthrough in a semiconductive material comprising the use of an electroforming solution and apparatus. In U.S. Pat. No. 4,394,712, there is disclosed a process for making a feedthrough in a semiconductor wafer array comprising three solid concentric materials including a central core of solder. In making the array, a plurality of the wafers are stacked and solder, which has been implanted in vias in the wafers and slightly beyond, is caused to flow, interconnecting the wafers.
The use of solid, dense feedthroughs to interconnect a plurality of wafers is typically costly and time consuming and makes it difficult to separate the wafers in the event that a wafer is or becomes defective and requires repair or replacement. The reason for this is that the heat required to form and/or sever the interconnections can be damaging to the wafers and the circuits located therein. Also, differential thermal coefficients of expansion between the rigid feedthroughs and the surrounding semiconductor and other materials can result in damaging stresses during thermal cycling.